This invention relates generally to electronic circuits. More particularly, this invention relates to reducing average power in SRAMs and DRAMs.
As more electronic circuits are included on a single die, the power dissipated by a single die continues to increase. In order to keep the temperature of a single IC (integrated circuit) at a reasonable temperature, many techniques have been used. For example, elaborate cooling fins have been attached to the substrate of ICs. Also, fans have been positioned near a group of IC""s to cool them. In some cases, liquids have been used to reduce the heat produced by ICs. These solutions can be costly and may require a great deal of space, where space is at a premium. If the power on ICs can be reduced while still achieving higher levels of integration, the cost and area of devices that use ICs may be reduced.
The number of bits contained on a semiconductor memory chip, has, on average, quadrupled every three years. As a result, the power that semiconductor memories consume has increased. Computer systems can use large numbers of stand-alone semiconductor memories. Part of the semiconductor memory used by these computer systems, may be held in standby mode for a certain amount of time. The portion of memory that is held in standby is not accessed for data and as result, has lower power requirements than those parts of semiconductor memory that are accessed. Part of the power used in stand-by mode is created by leakage current in each individual memory cell of the semiconductor memory. Because the amount of memory used in a computer system or as part of a microprocessor chip is increasing, the power, as result of leakage current in semiconductor memory cells, is also increasing. The following description of an apparatus and method for reducing the leakage current in semiconductor memory cells addresses a need in the art to reduce power in ICs and computer systems.
An embodiment of the invention provides a circuit for reducing power in SRAM and DRAM, (only DRAM cells that use a PFET (P-type Field Effect Transistor) transfer transistor) memory cells during standby. A variable voltage is electrically connected to Nwell areas that contain PFETs used in memory cells. During standby, the voltage applied to the Nwells containing PFETs used in memory cells is increased. The increase in voltage to the Nwell area increases the value of the Vt (threshold voltage) of the PFETs used in the memory cells. A higher Vt reduces the leakage current through the PFETs and as a result lowers the standby power of the memory cells. During normal operation (e.g. read and write operations), the voltage to the Nwell is lowered and as a result the Vt of the PFETs in the memory cells is lower. A lower Vt in the PFETs used in the memory cells allows the cells to be read or written faster.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.